Adding opcodes to the 6502 :)

More about Adding opcodes to the 6502 :)

The Apple 3 (usually known as the Apple ///) used a 2MHz 6502 with some bus-monitoring logic to add some extended addressing modes, allowing addressing beyond the standard 64K. Basically it monitored the current instruction and its addressing mode, and inserted a bus cycle to bank-switch to one of 7 (or 15?) blocks of 64K on built-in Apple RAM cards. Stupidly, Apple designed the Apple /// without full Apple ][ compatibility, so it could only emulate a 48K Apple ][, and did not allow a "language card" (Apple bank-switched RAM overlaying the system ROMs). I guess Apple did this to prevent loss of sales of the Apple ][.
Anyway, this gave me the idea of adding new opcodes to the 6502. Building a cheapo logic analyzer on a hobbyist Apple ][ card (Pete&Pam sold these, among other dealers) -- basically a 4118 static RAM taking its inputs from the data and address buses, and its address inputs from a local 74LS163(?) sequential counter (incremented on every bus cycle) allowed me to get a trace log of the micro-steps making up any 6502 instruction. (Look out for any opcode ending in $X2 -- they freeze the CPU!) Then we could program a PLA or FPLS to watch the bus for that sequence, and suspend the 6502 while we fiddled with the bus (I gather that's how the 80x87 FPU's work).
In the end we learned quite a lot about how things worked, and put that experience to practical use, producing a 68000 Coprocessor Card (the Aristocard).