::SHE+ILA::'s Microsequencer [$15]

More about ::SHE+ILA::'s Microsequencer [$15]

Here is a partial diagram of ::SHE+ILA::'s Microsequencer, the underlying logic that interprets ::SHE+ILA::'s instruction set. Box A (in purple) is a 32bit edge-triggered flipflop, (the microstate register), which provides the address inputs for Box B (in red), which is the writable control store (WCS). This contains the Microcode which defines the instruction set of ::SHE+ILA::. The output of B is latched by the microcommand register (not shown), which produces the control signals for the ALU (74LS181), accumulator (74LS374), register array (74LS89), and bus control. The remaining outputs of B feed back into A (the microstate register) to determine the next microstate (like a GOTO would work on a high-level language). Another cable from B (again not shown) connects to the host bus (Apple ][ or Pentium PC) via an 8T31 or 74LS374 in order to write the microcode into box B at bootstrap (startup) time. This allows use of fast static RAM (rather than slow EPROM) to implement box B, which speeds up the ::SHE+ILA:: microcode execution by a factor of 20 or more.